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K10 FPGA Kun Core Iris Recognition Chip – Chip-Level Hardware Platform for Large, Medium and Small-Scale Iris Encoding and Storage Management — Chips & SoCs by HOMSH Technologies
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Chips & SoCsID: 40680235

K10 FPGA Kun Core Iris Recognition Chip – Chip-Level Hardware Platform for Large, Medium and Small-Scale Iris Encoding and Storage Management

The K10 is an FPGA Kun Core iris recognition chip designed for chip-level iris encoding, storage, and matching. Features multi-core processing architecture with Gigabit and PCIe interfaces. Provides a scalable hardware platform for iris recognition systems of various capacities.

Key Specifications

Coding Kernel3
Coding Speed50 Sheets Per Second
Power Dissipation<10W
Support InterfaceGigabit Network, PCIe
Chip Package31 × 31mm
Production NameIris Recognition Chip
Encoding Kernels3
Encoding Speed50 images/second
InterfacesGigabit, PCIe
AlgorithmPhaseIris HW (proprietary)
Get a Quotesales@opticsiris.com
ISO 9001NIST TestedMPS Certified

About This Product

The K10 is an FPGA Kun Core iris recognition chip designed for chip-level iris encoding, storage, and matching. Features multi-core processing architecture with Gigabit and PCIe interfaces. Provides a scalable hardware platform for iris recognition systems of various capacities.

Category: Chips & SoCs
Brand: HOMSH / OpticIris
Origin: Wuhan, China

Order Information

Min. Order1 Unit
Delivery Time5-8 Working Days
PaymentT/T (Bank Transfer)
CertificationISO 9001

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